The concept xe2x80x9csystem LSIxe2x80x9d of a plurality of large-scale integrated circuits (LSIs) on a common substrate has recently been brought in and various methods of designing system LSIs have also been proposed. System LSIs in particular have the advantage of being realized as a wide variety of multifunctional semiconductor devices on an extremely large scale of integration in such a manner that a memory such as a dynamic random access memory (DRAM), a logic LSI, an analog circuit such as a high-frequency circuit, etc., are mounted in one semiconductor device.
As a method for testing each of such LSIs to determine whether the LSI is correctly formed, a built-in self-test (BIST), a scan test and a boundary scan test, for example, are known.
FIG. 24 is a block diagram for explaining a conventional ordinary built-in self-test (BIST). As shown in FIG. 24, a pattern generator for generating a test pattern, a result compressor and a control circuit are provided as BIST means in an LSI. The control circuit makes the test pattern generator generate a test pattern in response to a start signal and input the generated test pattern to a logic circuit which is a test object (DUT), and make the result compressor obtain a testing signal output from the test object and output the testing signal out of the LSI. An external instrument (tester) determines whether the test object logic circuit is operating normally. According to this testing method, a test can be automatically made without generating a pattern in a tester. This method has the advantage of using a smaller number of pins and imposing only an extremely small load on the tester.
FIG. 25 is a block diagram schematically showing an ordinary boundary scan test circuit. As shown in FIG. 25, the boundary scan test circuit has a scan chain formed by successively connecting flip flops (FFs) attached to external terminals of an LSI from an input test terminal (TDI) to an output test terminal (TDO). A test pattern is input to the scan chain to enable use of the boundary scan test circuit for determination as to whether connections between one LSI-A and an adjacent LSI-B are correctly made.
FIG. 26 is a block diagram showing an example of a configuration of a scan chain used in an ordinary scan test. Ordinarily, in a scan-in method, a scan chain test pattern is externally supplied and data output from a test object is immediately output from the test chain. That is, in ordinary cases of scan tests of internal circuits, no test pattern generator and no result compressor exist in the configuration shown in FIG. 24. However, scan-in may be used as a means for realizing a BIST.
FIG. 27 is a block diagram showing an example of a configuration of a flip flop provided in a boundary test circuit or a scan chain for a scan test of internal circuits.
The above-described conventional system LSIs are confronted with problems described below in actually forming devices.
The first problem resides in difficulty in reducing the device manufacturing cost. This is due to a high cost of development of system LSIs and a limited manufacturing yield.
The second problem resides in a considerable increase in wiring delay. In general, the height of devices is reduced in accordance with a shrinkage rule. With the reduction in sectional area of pieces of wiring, the wiring delay determined by RC (R is a resistance, and C is a parasitic capacitance) is increased. That is, as regards the wiring delay, the disadvantage of a design by a finer rule prevails over the advantage of the same. As a means for solving this problem, a buffer may be provided in wiring. However, if a buffer is provided, another problem arises in that the area occupied by a device and the power consumption of the device are increased.
The third problem resides in difficulty in reducing noise. If the power supply voltage is reduced, the current is increased and it is difficult to limit the increase in noise level corresponding to the increase in current. The S/N ratio becomes lower in proportion to the third to sixth power of the shrinkage rate. Thus, an increase in noise cannot be avoided when a finer design rule is used. That is, the point is how the power supply impedance is limited.
It is conceivable that a semiconductor device suitable for reduced-variety mass production is realized by mounting chip intellectual properties (IP) which are formed as integrated circuits by a plurality of various devices on a semiconductor wiring substrate having a wiring layer, e.g., a silicon wiring substrate. The chip IPs can be used as a means for realizing a semiconductor device incorporating multiple kinds of semiconductor devices having multiple functions while maintaining a large wiring piece sectional area.
However, there are no established means for mounting such chip IPs on a wiring substrate and for inspecting LSIs in the chip IPs. As mentioned above, the BIST method, the scan test method and the boundary scan test are known as conventional test methods. However, in a case where one of these test methods is used for testing of an IP On Super-Sub (IPOS) device, it has the drawback of requiring a considerably long test time if each of LSIs in chip IPs is separately tested after mounting of the chip IPs, and the drawback of being incapable of determination of defective/nondefective condition of wiring since there are no devices for receiving a signal on the wiring substrate before the chip IPs are provided.
An object of the present invention is to provide a semiconductor device in which chip IPs capable of being used as design properties are mounted on a common semiconductor wiring substrate, and which is designed so that each components can be easily inspected, and a method for inspecting the components of the semiconductor device.
To achieve the above-described object, according to a first device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a semiconductor substrate and a plurality of pieces of wiring formed on the semiconductor substrate, a plurality of chip IPs to be connected to the plurality of pieces of wiring being mounted on the semiconductor wiring substrate, an insulating layer formed on the pieces of wiring, and a boundary scan test circuit formed by a plurality of semiconductor elements provided on the insulating layer of the semiconductor wiring substrate, the boundary scan test circuit having connection points respectively connected to the plurality of pieces of wiring.
The semiconductor wiring substrate can be checked before mounting of the chip IPs to determine whether there is a defect in the wiring layer in the semiconductor wiring substrate.
If the above-described boundary scan test circuit is constituted by, for example, thin-film transistors (TFTs), it can be formed in the uppermost layer of the semiconductor wiring substrate.
According to a second device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a semiconductor substrate and a plurality of pieces of wiring formed on the semiconductor substrate, a plurality of chip IPs to be connected to the plurality of pieces of wiring being mounted on the semiconductor wiring substrate, a boundary scan test circuit provided in each of regions where the chip IPs are to be mounted, the boundary scan test circuit being constituted by a plurality of semiconductor element each having as its active region a portion of the semiconductor substrate of the semiconductor wiring substrate, the boundary scan test circuit being respectively connected to the plurality of pieces of wiring.
In this arrangement, the boundary scan test circuit can be formed below the chip IP mount regions, so that the entire area can be reduced.
According to a third device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a semiconductor substrate and a plurality of pieces of wiring formed on the semiconductor substrate, a plurality of chip IPs to be connected to the plurality of pieces of wiring being mounted on the semiconductor wiring substrate, an insulating layer formed on the pieces of wiring, and testing pads for testing the chip IPs, the testing pads being formed in a grid pattern on the semiconductor wiring substrate and individually connected to the plurality of pieces of wiring.
After mounting of the chip IPs on the semiconductor wiring substrate, each chip IP can be separately tested.
If the testing pads are formed in a grid pattern over the entire surface of the semiconductor wiring substrate, the semiconductor wiring substrate of the semiconductor device can adapted to chip IPs of any size.
According to a fourth device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a semiconductor substrate and a plurality of pieces of wiring formed on the semiconductor substrate, a plurality of chip IPs to be connected to the plurality of pieces of wiring being mounted on the semiconductor wiring substrate, and testing pads for testing the chip IPs, the testing pads being formed on the semiconductor wiring substrate and individually connected to the plurality of pieces of wiring. The above-described testing pads function as power supply pads only at the time of testing.
At the time of testing without consideration of power consumption, there is a possibility of all the chip IPs on the IPOS device operating at a time. Since the power consumption during ordinary operation is set to a smaller value, there is a risk of a malfunction resulting from lack of power when all the chip IPs in the IPOS device are operated for testing. In the arrangement of the present invention, additional power is supplied only at the time of testing to avoid lack of power.
According to a fifth device of the present invention, there is provided a semiconductor device having a semiconductor substrate on which a plurality of chip IPs are to be mounted, and a plurality of pieces of wiring formed on the semiconductor substrate to be used only for testing.
Therefore a semiconductor device based on a design suitable for facilitating testing can be obtained by using a semiconductor substrate having sufficiently large wiring formation regions.
Preferably, the pieces of wiring for testing only are connected to the pads for testing of the chip IPs provided on the semiconductor wiring substrate.
On the semiconductor substrate, a multilayer wiring layer may be formed in which a plurality of wiring layers and a plurality of insulating layers are alternately superposed. The pieces of wiring for testing only may be formed in one of the layers in the multilayer wiring layer below the uppermost layer, and may be located below the pads. Therefore this wiring structure can also be used in the case where the pads are formed in a grid pattern.
The above-described pieces of wiring for testing only may be formed in two of the above-described plurality of wiring layers so as to intersect with each other as seen in a plan view, and conductor portions are formable by dielectric breakdown between the testing pads and the two wiring layers at the points of intersection of the pieces of wiring. Thus, wiring routes can be formed as desired.
According to a sixth device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a wiring layer, a plurality of chip IPs mounted on the semiconductor wiring substrate by being bonded thereto, a boundary scan test circuit provided in each of the chip IPs, and an internal scan chain for an internal scan test. The scan chain is formed in each of the chip IPs and can operate simultaneously with the boundary scan test circuit.
If scan-in and scan-out terminals connected to the wiring in the wiring substrate are provided according to this arrangement, scan-in operation can be performed irrespective of the operation for the boundary scan test, so that the total test time can be reduced. In the IPOS device in particular, wiring to be used for a special purpose can easily be formed and the above-described testing circuit can therefore be formed easily.
At least one of scanning signal input terminals connected to the internal scan chain is a terminal specially formed separately from the boundary scan test circuit.
Thus, if scan-in and scan-out terminals connected to the wiring in the wiring substrate used for internally testing only, scan-in operation can be performed irrespective of the operation for the boundary scan test, so that the total test time can be reduced.
Each of in-chip chains in the boundary scan test circuit of the plurality of chip IPs is formed so as to also function as the internal scan chain in the chip IP. An input-side wiring branch and an output-side wiring branch which respectively branch off from an input-side end portion and an output-side end portion of the boundary scan test circuit are formed in each of the chip IPs. A scan-in terminal of the internal scan chain is connected to the input-side wiring branch, while a scan-out terminal of the internal scan chain is connected to the output-side wiring branch. An input to the in-chip chain can be selected from a signal in the boundary scan test circuit and a signal from the input-side wiring branch. Consequently, the boundary scan test and the scan test on the internal circuit can be speedily made.
According to a seventh device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a wiring layer, a plurality of chip IPs mounted on the semiconductor wiring substrate by being bonded thereto, a boundary scan test circuit provided in each of the chip IPs, at least two pieces of wiring formed in the wiring layer of the semiconductor wiring substrate to be used only for testing, and an input terminal and an output terminal for a boundary scan test connected to the boundary scan test circuit in each of the chip IP and respectively connected to the two pieces or wiring for testing only.
In this arrangement, a test pattern for the boundary scan test can be separately supplied to each chip IP, thus achieving a reduction in test time.
The boundary scan test circuit in the plurality of chip IPs is formed so to also function as an internal scan test circuit in the chip IPs. An input-side wiring branch and an output-side wiring branch which respectively branch off from an input-side end portion and an output-side end portion of the boundary scan test circuit are formed in each of the chip IPs. A scan-in terminal through which an internal scan test signal is input is connected to the input-side wiring branch. A scan-out terminal through which a scan test result is output is connected to the output-side wiring branch. Also, an input to the in-chip chain can be selected from a signal in the boundary scan test circuit and a signal from the wiring branch. Thus, it is possible to reduce the test time by changing the chain length between BST and BIST.
The boundary scan test circuit in the plurality of chip Ips is formed integrally with the internal scan chain in the wiring layer of semiconductor siring substrate. First special-purpose wiring for supplying a control signal supplied to the internal scan chain in each of the chip IPs and second special-purpose wiring for outputting a signal from the internal scan chain in each of the chip IPs are also provided. A scan-in terminal of the internal scan chain in each of the chip IPs is connected to the first special-purpose wiring, while a scan-out terminal of the internal scan chain in each of the chip IPs is connected to the second special-purpose wiring. Thus, the entire chain is not formed and the entire structure is simplified. This structure is particularly suitable for IPOS devices.
According to a first method of the present invention, there is provided a method for testing a semiconductor device including a logic circuit having a boundary scan test function and a built-in self-test (BIST) function, the method comprising combining a built-in logic block observer (BILBO) function with the boundary scan test function of the logic circuit, and making a boundary scan test and a built-in self-test (BIST) on the logic circuit.
This method enables a BILBO test to be made on peripheral portions outside the external terminals, where testing based on the conventional method is difficult.
According to still a second method of the present invention, there is provided a method for testing a semiconductor device including a logic circuit having a boundary scan test function and a built-in self-test (BIST) function, the method comprising providing a built-in logic block observer (BILBO) function in the logic circuit, and making a boundary scan test and a BIST on the logic circuit by supplying a linear feedback shift register (LFSR) signal as a boundary scan test signal to the logic circuit and by compressing boundary scan test results.
This method enables a BILBO test to be made on peripheral portions outside the external terminals.
According to still an eighth device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a wiring layer, a plurality of chip IPs mounted on the semiconductor wiring substrate by being bonded thereto, a scan test circuit provided in each of the chip IPs, the scan test circuit having a plurality of scan-in terminals and the same number of scan-out terminals as the number of the scan-in terminals, and a plurality of pieces of wiring formed in the wiring layer of the semiconductor wiring substrate to be used only for testing. A control signal is supplied to the scan test circuit of each of the chip IPs through the pieces of wiring. The number of the pieces of wiring is equal to the number of the scan-in terminals. The scan-in terminals of the scan test circuit in each of the chip IPs are respectively connected to the pieces of wiring for testing only.
This arrangement enables the scan test to be separately made on the internal circuit of each chip IP, thereby reducing the scan test time.
A gate may also be provided which is connected to each of the scan-in terminals. The gate sets an input to the scan-in terminals to a fixed value when a mode other than the scan test mode is selected. Thus, it is possible to reduce the power consumption by inhibiting the operation of the chip IPs other than the current test object.
According to a ninth device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a wiring layer, a plurality of chip IPs mounted on the semiconductor wiring substrate by being bonded thereto, a scan test circuit provided in each of the chip IPs, the scan test circuit having a plurality of scan-in terminals and the same number of scan-out terminals as the number of the scan-in terminals, and a plurality of pieces of wiring formed in the wiring layer of the semiconductor wiring substrate to be used only for testing. A control signal is supplied to the scan test circuit of each of the chip IPs through the pieces of wiring. The number of the pieces of wiring is equal to the number of the scan-out terminals. The scan-out terminals of the scan test circuit in each of the chip IPs are respectively connected to the pieces of wiring for testing only.
A gate may be further provided which is connected to each of the scan-out terminals and has a high-impedance when a mode other than a scan test mode is selected, thereby preventing mixing of test outputs from the ship IPs in the wiring for testing only.
According to a ninth device of the present invention, there is provided a semiconductor device including a semiconductor wiring substrate having a wiring layer, a plurality of chip IPs mounted on the semiconductor wiring substrate by being bonded thereto, a scan test circuit provided in each of the chip IPs, the scan test circuit having a plurality of scan-in terminals and the same number of scan-out terminals as the number of the scan-in terminals, and clock wiring formed in the wiring layer of the semiconductor wiring substrate, the clock wiring being used only for supplying a clock signal to the scan test circuit of each of the chip IPs. A clock terminal of the scan test circuit in each of the chip IPs is connected to the clock wiring.
Each chip IP is connected to the common clock wiring to enable the circuits in the chips IP to operate in synchronization with each other by a small clock skew.
According to a tenth device of the present invention, there is provided a semiconductor device comprising a semiconductor wiring substrate having a semiconductor substrate and a wiring layer formed on the semiconductor substrate, a plurality of chip IPs mounted on the semiconductor wiring substrate by being bonded thereto, and a test controller provided on the semiconductor wiring substrate for the purpose of controlling a circuit in each of the chip IPs.
The test controller is used to enable various tests to be easily made on each chip IP in the semiconductor device.
The above-described test controller may be constituted by a semiconductor element having a portion of the semiconductor substrate as its active region, or may be is provided as a chip IP on the semiconductor wiring substrate.
When the circuit in a first one of the plurality of chip IPs is separately tested by a scan method, if a boundary scan test circuit exists in the circuit in a second one of the chip IPs adjacent to the first one of the chip IPs, the test controller supplies a test pattern from an internal scan chain in the circuit in the first one of the chip IPs and executes an operation for connection to the boundary scan test circuit to simultaneously make the test on the circuit in the first one of the chip IPs and a test on the wiring between the first one of the chip IPs and the second one of the chip IPs, it can be determined, by using the boundary scan test circuit of the adjacent chip IPs, simultaneously, whether the internal circuit of the chip IP is defective or not, and whether the wiring connection states between the chip IP and adjacent chip IP is defective or not.
The circuit in each of the chip IPs has a linear feedback shift register (LFSR) function, a multiple input signature register (MISR) function and a BIST function. The test controller supplies a signal from a linear feedback shift register (LFSR) to a scan-in terminal of each of the chip IPs and makes a multiple input signature register (MISR) take in a signal from a scan-out terminal of each of the chip IPs. The functions necessary for the BIST on each chip IP are thus combined in one chip IP to enable centralized control of the test, thus achieving the effect of reducing the scale of the circuit in each chip IP.
The semiconductor device may further has a function for controlling the power supply voltage to each of the chip IPs, such that the test controller supplies the power supply voltage only to the circuit in the chip IP subjected to a test among the plurality of chip IPs and stops supply of the power supply voltages to the other chip IPs. This control makes it possible to reduce the power consumption at the time of testing and, hence, to prevent a malfunction of the components of each chip IP at the time of testing.
According to still a further aspect of the present invention, there is provided a mounting method for a semiconductor device, comprising a step (a) of mounting a plurality of chip IPs on a semiconductor wiring substrate having a wiring layer by bonding the chip IPs to the semiconductor wiring substrate, a step (b) of making a go-no-go test on the plurality of chip IPs and a step (c) of substituting another chip IP of the same type for the chip IP determined as a defective one in the step (b), and making the go-no-go test on the substituted chip IP. The step (c) is repeated until the substituted chip IP is determined as a nondefective one.
This method ensures improved reliability of the IPOS device and facilitate mounting of the components.